1. Field of the Invention
Generally, the present disclosure relates to the manufacture of integrated circuit products, and, more specifically, to various methods of forming air gaps in metallization layers on integrated circuit products.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years, particularly the channel length of transistor devices. As a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections or “wiring arrangement” for the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured. Accordingly, the various electrical connections that constitute the overall wiring pattern for the integrated circuit product are formed in one or more additional stacked so-called “metallization layers” that are formed above the device level of the product. These metallization layers are typically comprised of layers of insulating material with conductive metal lines and conductive vias formed in the layers of material. Generally, the conductive lines provide the intra-level electrical connections, while the conductive vias provide the inter-level connections or vertical connections between different levels. These conductive lines and conductive vias may be comprised of a variety of different materials, e.g., copper, with appropriate barrier layers, etc. The first metallization layer in an integrated circuit product is typically referred to as the “M1” layer, while the conductive vias that are used to establish electrical connection between the M1 layer and lower level conductive structures (explained more fully below) are typically referred to as “V0” vias. The conductive lines and conductive vias in these metallization layers are typically comprised of copper, and they are formed in layers of insulating material using known damascene or dual-damascene techniques. Additional metallization layers are formed above the M1 layer, e.g., M2/V1, M3/V2, etc. Within the industry, conductive structures below the V0 level are generally considered to be “device-level” contacts or simply “contacts,” as they contact the “device” (e.g., a transistor) that is formed in the silicon substrate.
The continuous reduction of the feature sizes of transistors, and the associated improvement in the performance of such transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system used to electrically connect all of the actual semiconductor-based circuit elements, such as transistors, that are formed in and above the semiconductor substrate. That is, signal propagation delay may no longer be limited by the field effect transistors but is limited, owing to the increased circuit density, by the interconnect lines in the metallization layers, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. Thus, reduction of the parasitic RC time constants and the capacitive coupling between neighboring metal lines is an ongoing issue when manufacturing integrated circuit products.
In earlier product generations, the metallization layers in integrated circuit products were typically comprised of silicon dioxide and/or silicon nitride, with aluminum as the typical metal. In more recent products, copper has been used instead of aluminum for the material of the conductive lines due to the significantly lower electrical resistance and a higher resistivity against electromigration of copper as compared to aluminum. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less.
In addition to using such low-k materials, another technique that device designers have employed to reduce the capacitive coupling between the conductive lines in metallization layers involves the intentional formation of air gaps in the insulating materials in those metallization layers. Air or similar gases have a dielectric constant of approximately 1.0, thereby providing reduced overall permittivity of the interconnect system. FIGS. 1A-1F depict one illustrative prior art technique employed to form air gaps in metallization layers.
FIG. 1A depicts a prior art integrated circuit product 10 that is formed in and above a semiconductor substrate 12. Also depicted is an ILD layer 14, e.g., silicon dioxide. The ILD layer 14 is formed on and above the individual semiconductor devices (not shown), such as transistors. Also depicted is an illustrative metallization layer comprised of a layer of insulating material 16, e.g., silicon dioxide or a low-k material, and a patterned layer of silicon nitride 18 that acts as an etch mask when forming the trenches 20 in the layer of insulating material 16. The metallization layer shown in FIG. 1A is representative of any of the metallization layers that may be formed above the substrate 12, e.g., the M1 layer, M2, M7, etc. At the point of processing depicted in FIG. 1A, a plurality of trenches 20 have been formed by performing a plurality of traditional masking and etching processes. Eventually, conductive metal lines, e.g., copper lines, will be formed in the trenches 20.
FIG. 1B depicts the product after illustrative and simplistically depicted conducting lines 22 (e.g., copper lines) were formed in the trenches 20. The conductive lines 22 typically also include one or more barrier layers (not separately shown) that are formed between the insulating material and the copper material of the lines 22 to prevent or reduce electromigation of the copper material. In the case where the lines are comprised of copper, a typical process of forming the lines 22 includes the following steps. First, a conformal barrier layer is deposited on the product such that it lines the bottom surface and sidewalls of the trenches 20. Next, a thin copper seed layer is formed on the product, followed by performing an electroplating process to deposit bulk copper material in such quantities that it overfills the trenches 20. Thereafter, one or more chemical mechanical polishing (CMP) processes are performed to remove excess conductive material positioned outside of the trenches 20. These CMP processes also remove the layer 18.
FIG. 1C depicts the product 10 after a selective deposition process was performed to selectively form a conductive cap layer 24, e.g., cobalt on the conductive lines 22.
FIG. 1D depicts the product 10 after a timed, recess etching process was performed on the layer of insulating material 16 to reduce its thickness and thereby expose portions of the conductive lines 22. The amount of recessing of the insulating material 16 may vary depending upon the particular application.
FIG. 1E depicts the product 10 after a conformal deposition process was performed to form a relatively thin etch stop layer 26, e.g., silicon nitride, on the product 10 and particularly on the conductive lines 22.
FIG. 1F depicts the product 10 after a layer of material 28 was formed on the product 10 and after a CMP process was performed to planarize its upper surface. The layer of material 28 may be comprised of a material such as silicon nitride, and it may be formed to a thickness of about 10-30 nm. The lateral spacing between the conductive lines 22 is small enough (e.g., 20-40 nm) such that the layer of material 28 does not fill a substantial portion of that lateral space. This results in the formation of air gaps 30 between the adjacent conductive lines 22. While the process shown in FIGS. 1A-1F can be employed to form air gaps, it can be very challenging to integrate.
The present disclosure is directed to various methods of forming air gaps in metallization layers on integrated circuit products that may solve or reduce one or more of the problems identified above.